1. Technical Field
The present invention relates generally to signal interfaces, and in particular to an adjustable digital signal receiver. More particularly, the present invention relates to a circuit and device for adjustably setting switch points in a digital signal receiver in a hysterisis or anti-hysterisis mode.
2. Description of the Related Art
In addition to on-board processing, storage and logic modules, digital hardware devices such as integrated circuit (IC) chips typically include signal coupling interface circuitry to facilitate reliable, high-frequency inter-device signaling. Digital signal receivers/detectors are commonly included among such inter-module signaling interface devices. In general, a digital signal receiver includes circuit means for detecting a digital signal from a noisy input signal and re-generating the signal to remove noise or other signal distortion that may be introduced over a transmission path. As utilized in a chip-to-chip digital transmission application, a digital signal receiver performs a signal detection function for eliminating or minimizing signal distortion introduced over a signal line across a printed circuit board.
Fundamentally, a digital signal receiver includes circuit means for distinguishing between the binary signal levels. To this end, the receiver comprises detection means for determining the point in time and direction of the logic level transitions. Accurate detection and regeneration of a received digital signal therefore requires correspondingly accurate detection of the signal transition threshold levels or switch points. A common type of digital signal receiver employs reference level comparison techniques for determining the switch point of an incoming digital signal. Generally, a comparator or differential-type receiver includes a Vref level which is compared with the incoming signal to detect the switch points. However, maintaining DC reference levels within each of many onboard digital signal receivers presents substantial thermal dissipation problems given the increasing number and speed of current inter-chip signaling bus connections.
Another approach to detecting digital signals utilizes basic complementary metal oxide semiconductor (CMOS) inverter technology to reconstitute an incoming signal that may be degraded such as by rolloff. As is well-known in the art, a basic CMOS inverter comprises complementary logic devices in the form of a P-type field effect transistor (PFET) pull-up net source-to-drain coupled to an N-field effect transistor (NFET) pull-down net. Its complementary design enables a CMOS inverter to detect and switch at approximately the mid-transition voltage level of the input signal. However, accurate switch point detection requires precise correspondence between the inverter switch point and the received signal transition midpoint, such as vdd/2. Therefore, even slight manufacturing variations or runtime operating variations over temperature or device wear can introduce significant distortion in received signal detection. Furthermore, conventional CMOS type digital receivers are unable to compensate for shifts in the incoming signal level caused by noise or other system environmental factors. Even a very slight DC shift in the incoming signal may result in significant distortion even with a precisely manufactured CMOS receiver.
Attempts to address the foregoing problems relating to device and/or environmental signal distortions factors and the desire for high-speed, low-power characteristics of CMOS has led to the development of “elastic” interfaces, in which the timing of the individual signal line receiver circuits can be adjusted to accommodate the individual line variations and device tolerances. An example of such a receiver design is described in U.S. Pat. No. 6,084,426, issued to Allen. The receiver disclosed by Allen is a compensated CMOS receiver comprising an inverter having controllable compensation legs that enables the receiver switch point to be adjusted in conformity with a target reference switch point level.
While addressing some of the foregoing issues, the tunable receiver disclosed by Allen does not adequately address problems relating to intermittent noise or signal disturbances. Furthermore, a noisy high-speed link may require almost continuous “recalibrations” using the technique disclosed by Allen, thus increasing the signal processing required for switch point adjustment as well as the likelihood of recalibration errors.
It can therefore be appreciated that a need exists for a digital signal receiver device and system that overcomes the foregoing problems. The present invention addresses these and other needs unresolved by the prior art.